A semiconductor device is produced by repeating a process of transferring, on a semiconductor wafer, a pattern formed on a photomask through lithographing and etching. In the semiconductor device production process, quality of the lithographing, etching, or other processing, presence/absence of occurrence of foreign matters, and the like significantly influence yield of the semiconductor device. Thus, in order to detect occurrence of such abnormality or defect in the production process in an early stage or in advance, the pattern on the semiconductor wafer is measured or inspected during the production process.
Particularly, along with recent advancement of miniaturization and three-dimensionalization of the semiconductor device, management of pattern superposition between different processes has become increasingly important. In a conventional approach, a position of the pattern formed in each process is measured from a reflecting light obtained by irradiating the semiconductor device through a dedicated pattern with light, whereby a superposition error of the pattern between different processes is calculated.
However, there is now required a more highly accurate superposition management due to decrease in a superposition tolerance associated with the miniaturization of the semiconductor. Although only an offset amount of the whole shot is managed for each shot in the conventional approach, a variation in the superposition misalignment amount in each shot caused by characteristics of an exposure device cannot be ignored at present. Further, there is a need to take into consideration influence of a machining process other than the exposure, such as inclination of an etching hole.
To respond to such a need, a superposition measuring means that uses an actual process pattern of the semiconductor device by a scanning electron microscope (SEM) is proposed. For example, PTL 1 describes a technology that measures a superposition error between different layers using the scanning electron microscope.